System for the transmission of data via a differential bus

ABSTRACT

The transmission of data via a differential bus by means of balanced signals is not only reliable, but also offers the advantage that in the event of various single faults, i.e. faults concerning only one of the two lines or faults where the two lines of the differential bus are short-circuited, data transmission is still possible, be it with a reduced reliability. To this end, both lines are connected to a number of comparators which have different threshold values so that the nature of a fault occurring can be determined and, in dependence thereon, the comparator output can be determined wherefrom the recovered data signal must be derived.

BACKGROUND OF THE INVENTION

The invention relates to a system for the transmission of binary databetween a number of stations which are interconnected via a common firstline and a common second line, the first line having a low potential andthe second line a high potential for one logic value of the binary datawhereas the first line has a high potential and the second line a lowpotential for the other logic value of the binary data, the logic valueof the binary data being derived from the potential of at least one linefor output on a data output.

SUMMARY OF THE INVENTION

The lines used in such systems for the transmission of data are oftenreferred to as a differential bus, because the logic value of thetransmitted binary data is represented by the difference between thepotentials on the two lines, taking into account the sign of thedifference. Such a differential bus offers the advantage that extraneouselectromagnetic disturbances influence the potentials on the two linesin essentially the same way, so that the difference between thepotentials remains substantially the same. This results in a veryreliable data transmission. Moreover, the electromagnetic disturbancesemitted by the two lines upon potential transitions essentiallycompensate one another.

Systems comprising a plurality of stations interconnected via adifferential bus are often used in an environment in which the two linesare also subjected to notably mechanical loading, so that they areliable to be damaged. An example in this respect is the use of such asystem in motor vehicles. Moreover, the two lines also extend at leastpartly very close to grounded metallic components.

EP 0 529 602 A3 discloses a receiver circuit whereby signals can bereceived and evaluated even if one of the lines is disturbed. For thispurpose use is made of three comparators, each of which is succeeded bya counter and an AND-gate. One comparator compares the signals on thetwo lines with one another and hence operates for the non-disturbedcase, whereas the other two comparators compare the signals on arespective line with a fixed threshold value so that in the case of adisturbance of one of the lines the signals on the other line alone canstill be evaluated. The counters serve as timers which drive theassociated AND-gate and inhibit the passing on of the high output signalof the comparator if the duration thereof exceeds a predetermined periodof time. The AND-gates are succeeded by a selection circuit whose outputsupplies the output signals of the one comparator for the evaluation ofthe signal difference between the two lines if such output signals aregenerated, i.e. if the lines are not disturbed, and which otherwisedelivers the output signals of the other comparators on its output. Inthe case of given line faults and signals, some signals may be lost,i.e. not be evaluated, due to the delayed blocking of the AND-gates andthe switching operations in the selection circuit in response to theoccurrence of a fault, so that the entire message must be repeated.

Therefore, it is an object of the invention to provide a system of thekind set forth in which data transmission without data loss is alsopossible in the case of given damage to at least one of the two lines,be it with a lower transmission reliability.

This object is achieved in accordance with the invention in that in atleast a first station there is provided at least one first comparatorwhich is coupled to both lines in order to subtract the potential on thefirst line from the potential on the second line and to output an outputsignal of a first value via a first comparator output if the differenceformed by the subtraction exceeds a first threshold value, said firstthreshold value being chosen so that the output signal of the firstcomparator also changes its value if a potential transition occurs ononly one of the two lines and the other line has a potentialcorresponding to the one logic value of the binary data.

As a result of the use of a comparator which forms not only thedifference between the potentials on the two lines but also comparesthis difference with a given first threshold value, the transmitted datasignal is also reproduced on the output of this comparator if one of thetwo lines is interrupted. Because, as is known, each line is connectedto a low potential or a high potential via a resistor in such a mannerthat the potentials on the line correspond to the one logic value of thebinary data if none of the stations applies a signal to the lines, andbecause these resistors are preferably provided for each station, aninterrupted line has a substantially defined potential so that the noneinterrupted line can still be used for the transmission of data. Becauseof the steps taken in accordance with the invention, an interruption ofonly one line does not yet disturb the data transmission. A connectionbetween the first line and a grounded metal component, i.e. a groundshort circuit of the first line, does not yet disturb the datatransmission either.

The described faults, notably an interruption of one of the two lines,may be considered to be the most probable faults. However, other faultsare also feasible; notably the second line may also come into contactwith a grounded metal component, or the two lines could beshort-circuited to one another. In order to enable data transmission inprinciple even in such cases, an embodiment of the invention ischaracterized in that in each first station there is provided a secondcomparator which is coupled to the first line in order to generate anoutput signal of the first value on a second comparator output if thepotential on the first line exceeds a second threshold value, and thatthere is provided a first memory which is coupled to the firstcomparator output via a first delay member having a first delay time, anoutput of said memory being coupled to a switch for switching the dataoutput from the first comparator output to the second comparator outputif the output signal on the first comparator output continuously has thefirst value for a period of time corresponding to the first delay time.

In the case of these faults, however, non-disturbed data transmissioncannot take place at the instant of occurrence of the fault; a givenperiod of time is then required so as to carry out the necessaryswitching. This is because transmission of data signals withoutsimultaneous transmission of a clock signal must take place in such amanner that the clock signal can be derived from the data signal or isgiven for all stations. For this purpose there are a number of differentcodes (for example, NRZ modulation) enabling the failure of a normaldata signal to be recognized already after a few clock periods. In thiscase the delay time may be chosen so as to be short, so that switchingcan take place rapidly. In the case of other codes, however, the logicvalue of the data signals is formed by a continuous signal so thatsuccessive data of the same logic value form a constant signal withoutsignal transitions, the signal transitions being used only forsynchronizing a clock generator at the receiver end. Special encodingsteps then ensure that the number of successive data of the same logicvalue does not exceed a maximum number. In this case the first delaytime must be chosen to be longer than the duration of the maximum numberof successive same data at the lowest transmission frequency. If one ofthe latter two faults occurs directly after a signal transition or apotential transition on the two lines, the data subsequently transmittedduring the first delay time is substantially lost. However, in mostcases this can be compensated for by repeating the transmission of adata block which was being transmitted when the fault occurred, forexample because the receiver has not acknowledged the disturbance-freereception of the data block.

It is desirable that the elimination of a fault during a datatransmission does not cause a disturbance, if at all possible.Disappearance of the fault can occur, for example because a connectionwithin one of the lines makes poor contact or because a groundshort-circuit or a connection between the two lines disappears again dueto mechanical shocks. For the first three faults disappearance andappearance have hardly any effect on the data transmission itself; onlythe reliability is enhanced again after the disappearance of such afault. Disappearance of the last two faults switches the memory backagain. However, in order to prevent brief disturbance signals on thelines from unduly switching back the memory, the first memory in eachfirst station is preferably also coupled, via a second delay memberhaving a second delay time, to the first comparator output in such amanner that the first memory switches over the switch in such a mannerthat the data output is switched back from the second comparator outputto the first comparator output if the output signal on the firstcomparator output does not have the first value for a period of timecorresponding to the second delay time.

It is thus reliably ensured that the first memory is not unduly switchedback to the normal state by the disturbance signals.

In many cases not all stations, or even none of the stations, of thedescribed system comprise their own power supply; instead, parallel tothe two lines for the data transmission there is provided at least onefurther line which carries a supply voltage wherefrom a lower operatingvoltage is derived in each station for operation of an electric circuitin the station in order to drive the first and the second line. It maythen occur that a fault brings the first or the second line into contactwith the third line so that the potential on the relevant line becomesequal to the supply voltage. In order to enable data transmission viathe non-disturbed line even in such a case, a further embodiment of theinvention is characterized in that in each first station belonging tothe stations thus powered there are provided a third, a fourth and afifth comparator, the third comparator being coupled to the second linein order to generate an output signal of the first value on a thirdcomparator output if the potential on the second line exceeds a thirdthreshold value, the fourth comparator being coupled to the first lineand the fifth comparator being coupled to the second line, each of thelatter two comparators generating an output signal of a first value on afourth and a fifth comparator output, respectively, if the potential onthe line coupled to the relevant comparator exceeds a fourth thresholdvalue which is valued between the operating voltage and the supplyvoltage, that there are provided a second and a third memory, each ofwhich comprises a first input and a second input and an output, thefirst input of the second memory being coupled to the first comparatoroutput, the second input of the second memory to the fourth comparatoroutput, the first input of the third memory to the fifth comparatoroutput, and the second input of the third memory being coupled to thefifth comparator output via a third delay member having a third delaytime, and that the output of the second memory is coupled to the switchso as to couple the third comparator output to the data output, theoutput of the third memory being coupled to the switch so as to couplethe second comparator output to the data output.

The fourth and the fifth comparator can immediately detect whether oneof the two lines is short-circuited to the higher operating voltage. Inthe case of the first line the effect of such a short-circuit is as ifthis line continuously carries at least a potential corresponding to thesecond logic value of a binary data signal, so that the first comparatorcontinuously supplies an output signal of the first value. Therefore, inthis case the data output is coupled to the third comparator outputwhich evaluates the signal on the second line which is assumed to beoperational. However, if the second line is short-circuited to thesupply voltage, the difference between this potential and the potentialon the non-damaged first line is so negative that the threshold value ofthe first comparator is never exceeded and the signal on the firstcomparator output never assumes the first value. Therefore, in this casethe data output is coupled to the second comparator output whichevaluates the potential on the first line which is assumed to benon-damaged. It is again effective to couple the inputs of the memoriesto the corresponding comparator outputs via delay elements in order toprevent malfunctioning due to brief disturbance signals.

Generally speaking, it does not suffice that despite a fault datatransmission is still possible on one of the two lines of thedifferential bus; such a fault should also be signaled to theenvironment via a fault indication output so that the fault can beremoved. With the exception of the first three fault cases, in responseto faults memories are switched over whose output signals can be usedfor fault indication. For the first three faults, however, additionalfault detection is necessary. To this end, a further embodiment of theinvention is characterized in that in each first station there areprovided a first and a second counter, each of which comprises a countinput, a reset input and a count output, the count input of bothcounters being coupled to the first comparator output, the reset inputof the first counter to the second comparator output, the reset input ofthe second counter to the third comparator output, and the count outputof both counters as well as the output of the storage members beingcoupled to the fault indication output. Each counter thus counts anumber of signal transitions of the first comparator output and in thefault-free case with each such signal transition there is associated acorresponding signal transition on the second and on the thirdcomparator output, so that the counters cannot count beyond theirinitial position. However, should one of the two lines be disturbed, thesignal transitions will be absent on the corresponding second or thirdcomparator output, so that the relevant counter can reach a faultposition in which a fault signal is generated.

At least in stations which not only are capable of receiving but also oftransmitting data each line is coupled, via an associated switch, to thepotential for the other logic value of the binary data. Moreover, thereis provided a drive circuit which in the fault-free case closes the twoswitches for the transmission of said other logic value of the binarydata. However, if in the case of a fault, for example, one of the linesis low-impedance connected to a voltage which deviates from thepotential corresponding to the other logic value, which deviation isdetected upon reception of data, during the subsequent transmission theassociated switch would establish a short-circuit between this potentialand the voltage whereto the line is connected. This causes a higherpower loss at the switch and higher loading of the voltage sourcepowering the system or at least a few stations. In order to avoid thissituation, the drive circuit is constructed so that it prevents theclosing of the relevant switch in at least some fault cases.

As has already been stated, each of the two lines is connected, via arespective resistor, to another potential or another voltage definingthe one value of the binary data on the lines. In one fault case, whereone line is short-circuited to the voltage corresponding to the othervalue of the binary data or to the supply voltage or to the other line,a current flows continuously through the relevant resistor, or throughboth resistors, said current causing an increased power loss and higherloading of the power supply for the system. In order to avoid thissituation, switches are preferably connected in series with bothresistors in each station, said switches being opened in given faultcases. The output signals of the comparators, or of the memoriessucceeding these comparators, can be simply used to drive the switches.

In systems with a limited electric power, for example battery-poweredsystems as used in a motor vehicle, it is advantageous to provide astation standby state in which the power consumption is substantiallyreduced, for example by switching off the major part of the circuit ineach station. The lines, however, in this state must have the samepotentials as in the active state in order to ensure that a station canbe set to the active state by a potential variation on the lines, i.e.the lines must still be connected to the corresponding potentials viathe resistors. An increased power loss in the case of a fault would nowbe an even greater problem, so that for given faults it is absolutelynecessary to disconnect the relevant resistor. For this purpose thereare provided at least two further comparators which are active in thestandby state and control the switches in series with the resistors.

The invention also relates to a station for use in the system accordingto the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

Embodiments of the invention will be described in detail hereinafterwith reference to the drawing. Therein:

FIG. 1 shows diagrammatically a system comprising a plurality ofstations plus their line connections,

FIG. 2 shows a block diagram of the essential parts of a station,

FIG. 3 shows a block diagram of one of the two fault detection circuits,

FIG. 4 shows a block diagram of the further fault detection circuit,

FIG. 5 illustrates the control of the data output and the terminatingresistors,

FIG. 6 shows the circuit diagram of a station for a standby state,

FIG. 7 shows a further fault detection circuit for the standby state.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows diagrammatically three stations 1, 2 and 3 which areinterconnected via three lines 11, 12 and 13. The line 13 is in thiscase connected to a higher supply voltage wherefrom the individualstations derive the operating voltage for the electronic circuitaccommodated therein. The lines 11 and 12 constitute the differentialbus via which the data is transmitted.

Further details are shown for the station 2 but have been omitted forthe stations 1 and 3 for the sake of clarity. The line 11 is connectedto ground via a resistor 14 and a switch. The line 12 is connected, viaa resistor 15 and a further switch, to the operating voltage Vc which isderived from the supply voltage on the line 13 in the station. Thefunction of the two, normally-closed switches will be described indetail hereinafter. Furthermore, the station 2 comprises a controldevice 5 which drives two switches 6 and 7 together, the switch 6connecting the line 11 to the operating voltage Vc whereas the switch 7connects the line 12 to ground. When the switches 6 and 7 are open, theline 11 carries a low potential, via the resistor 14, and the line 12carries the operating voltage Vc via the resistor 15. This at the sametime corresponds to the one logic value of the binary data signals to betransmitted. If the other logic value is to be transmitted, the controlunit 5 closes both switches 6 and 7 so that the line 11 carries a highpotential and the line 12 carries a low potential. Each of the stations1 to 3 can thus transmit data via the lines 11 and 12. The state, or thepotentials, on the lines 11 and 12 in the case of open switches 6 and 7,therefore, will be referred to as the recessive state hereinafter andthe state in the case of closed switches 6 and 7 as the dominant state.

It is to be noted that instead of being connected to ground and to theoperating voltage Vc, the lines 11 and 12 can also be connected to avoltage slightly higher than ground and slightly lower than Vc,respectively, via the switches, for as long as the difference betweenthe two voltages remains large enough.

FIG. 2 shows the circuit for evaluating the data transmitted via thelines 11 and 12 in a station. Both lines 11 and 12 are connected to afirst comparator 21 which forms the difference between the potentials onthe lines 11 and 12; more exactly speaking, it subtracts the potentialon the line 12 from that on the line 11 and compares the difference ofcorrect sign with a first threshold value. This threshold value ischosen so that a low output signal is generated on the line 31 only inthe recessive state of both lines 11 and 12. The line 31 is connected toa multiplexer 29 which switches the line 31 to the data output 40 in thefault-free case and in given fault cases. The line 31 is also connectedto two fault detection circuits 26 and 27 which will be described indetail hereinafter.

The line 11 is also connected to a comparator 22 which compares thepotential on this line with a threshold value which is valued, takinginto account tolerances, between the dominant and the recessivepotential on the line 11. The comparator 22 generates a high signal onthe line 32 if the potential on the line 11 exceeds the threshold value.The line 32 is connected to the fault detection circuit 26 as well as tothe circuit 29 which connects this line to the data output 40 in givenfault cases.

The line 11 is also connected to a further comparator 24 which comparesthe potential on this line with a voltage valued between the operatingvoltage of the circuit and the higher supply voltage on the line 13 inFIG. 1 and generates a signal on the line 34 if the potential on theline 11 exceeds the operating voltage. The line 34 is connected to thelower fault detection circuit 27.

Analogously, the line 12 is also connected to a comparator 23 whichcompares the potential on this line with a threshold value which is alsovalued between the dominant and the recessive potential. The comparator23 generates a high signal on the line 33 if the potential on the line12 is below the threshold value. The line 33 is connected to the upperfault detection circuit 26 and to the circuit 29 which connects thisline to the data output in a given fault case as will be described indetail hereinafter.

The line 12 is also connected to a comparator 25 which compares thepotential on this line with a threshold value which is valued betweenthe operating voltage and the higher supply voltage, in the same waythat is to say as in the comparator 24 for the potential on the line 11.The output line of the comparator 25 is also connected to the lowerfault detection circuit 27. In case the operating voltage is applieddirectly to the individual stations instead of a higher supply voltageon the line 13, a short-circuit between the line 12 and the operatingvoltage will have the effect of an interruption of the line 12 so thatit can also be dealt with as such.

The upper fault detection circuit 26 generates a fault signal on anoutput line 36a if the line 11 is interrupted or short-circuited toground. A fault signal is generated on the line 36b if the line 12 isinterrupted.

The lower fault detection circuit 27 generates a signal on an outputline 37 if the two lines 11 and 12 are short-circuited to one another orif the line 12 is short-circuited to ground or if the line 11 isshort-circuited to the supply voltage. In this case a fault signal isalso generated on the line 38. A fault signal is generated on the line39 if the line 12 is short-circuited to the supply voltage.

All fault signals on the lines 36a, 36b and 37 to 39 are combined by acombinatory element 30 so as to be output via a fault indication output41.

The lines 37 to 39 are also connected to a priority circuit 28 becausein given fault cases more than one line carries a high signal butunambiguous control signals are required for the circuit 29nevertheless. The line 38 has the highest priority; the line 39 has thehighest priority but one, and the line 37 has the lowest priority. Theconstruction of such a priority circuit 28 is generally known. Thesignals on the lines 37 to 39 are indicated in conformity wit theirpriority on the lines 37a to 39a.

The circuit 29 also includes switches, as indicated in the station 2 inFIG. 1, which connect the resistor 14, connected to the line 11, toground and the resistor 15, connected to the line 12, to the operatingvoltage Vc.

The signals of the lines 37a to 39a can also be used to block thedriving of the switches 6 or 7 in FIG. 1. For example, if the line 11 orthe line 12 is short-circuited to the supply voltage on the line 13,driving of the switches 6 or 7 would establish a connection between thesupply voltage and ground or the operating voltage. Depending on theratio of the short-circuit resistance to the switch-on resistance of theswitch, a high power loss occurs thereon. A signal on the line 38a(short-circuiting of the line 11 to the supply voltage), therefore,blocks the driving of the switch 6. Analogously, a signal on the line37a (line 12 short-circuited to the line 11) or on the line 39a (line 12short-circuited to the supply voltage) blocks the driving of the switch7. A signal also occurs on the line 37a in the case which is notcritical to the switch 7, i.e. the case where the line 12 isshort-circuited to ground, but the blocking of the driving of the switch7 is not a drawback in this case. On the other hand, in case the line 11is short-circuited to ground, causing a signal on the line 36a, a higherpower loss occurs on the switch 6, so that this switch should also beswitched off in the event of this fault. The signal on the line 36a,however, also occurs in the case of an interruption of the line 11, inwhich case the switch 6 should then be driven further so as to ensurethat elimination of this fault is directly recognized. If these twofaults of the line 11 are not distinguished, requiring an additionalexpenditure, the driving of the switch 6 should not be blocked when theline 11 is short-circuited to ground.

FIG. 3 is a more detailed representation of the construction of thefault detection circuit 26 of FIG. 2. It includes two counters 51 and54, two differentiating circuits 52 and 55 as well as two countingmemories 53 and 56. The counting inputs of the counters 51 and 54 areconnected together to the line 31. The input of the differentiator 52 isconnected to the line 32, and the differentiator 52 outputs a briefoutput signal if a signal edge occurs on the line 32 due to thetransition of the signal on the line 11, and the signal from thedifferentiator 52 resets the counter 51 to an initial position and alsosets the counting memory 53 to its rest state. The differentiatingcircuit 55 receives the signal from the line 33 and generates, on thebasis of the signal transition occurring on the line 33 in response tothe transition on the line 12, a brief output signal which sets thecounter 54 to an initial position and the counting memory 56 to the reststate.

If the line 11 or 12 is interrupted, signal transitions still occur onthe line 31 and are counted by the two counters 51 and 54; however,depending on the interrupted line, no corresponding signal transitionoccurs on the line 32 or the line 33, so that the associated counter 51or 54 is not reset but reaches a count at which the counting memory 53or 56 is set. A fault signal is thus generated on the corresponding line36a or 36b. Instead of using the counting memories 53 and 56, it is alsopossible to block the further counting by the counters when they reachthe corresponding count. If the fault disappears or has been removed, acounting memory in the set state or a blocked counter is automaticallyreset, because in that case signal edges occur again on both lines 32and 33.

The construction of the fault detection circuit 27 of FIG. 2 is shown ingreater detail in FIG. 4. It comprises three memories 61, 62 and 63,each of which is composed of two cross-coupled NOR-gates, the furtherinputs of the NOR-gates constituting the inputs of the memory. For thesake of clarity, however, the construction is shown only for the memory61. Use can also be made of other, so-called R-S flipflops.

The upper input of the memory 61 is connected to the line 31 via a firstdelay member 64. As soon as the line 31 carries a high signal for acontinuous period of time which is longer than the delay time of thefirst delay member, the output of the delay member 64 becomes high and ahigh signal is generated on the output line 37. This persistent highsignal appears on the line 31 if one of the two lines is continuously ina dominant state due to a fault. This is the case if the two lines areshort-circuited to one another, because in that case the two lines donot simultaneously have a recessive state at any instant and the signalon the line 31 does not become low. The delay time of the delay member64, therefore, must be longer than the maximum duration of a maximumnumber of transmitted data of the same value.

If such a fault has been removed and the signal appears on the line 31in the case of a recessive state on both lines 11 and 12, the memory 61is reset again via an inverter 65 and a further delay member 66 which isconnected to the lower input of the memory 61, and the signal on theline 37 is made low. The delay member 66 serves to prevent undueresetting of the memory 61 by brief disturbance signals in the case of afault.

One input of the memory 62 is connected to the line 34, via a delaymember 67, and its other input is connected to the delay member 66. Thetwo delay members preferably have approximately the same delay time. Assoon as the line 11 is short-circuited to the supply voltage, a highsignal appears on the line 34 and, if this signal prevails for a periodof time which is longer than the delay time of the delay member 67, thememory 62 is set and a high signal is generated on the line 38. Thisstate is the dominant state of the line 11 and as long as this stateprevails no signal transitions are produced on the line 31, so that thememory 62 remains set. It is only after the fault has been removed andsignals appear again on the line 31 that the memory 62 is reset, so thatthe signal on the line 38 then becomes low again. However, the resettingof the memory 62 can alternatively be realized by the signal on the line34 via an inverter (not shown).

Via a delay member 68, one input of the memory 63 is connected to theline 35 which carries a high signal if the line 12 is short-circuited tothe supply voltage. If the duration of this short-circuit is longer thanthe delay time of the delay member 68, preferably being approximatelyequal to the delay time of the delay members 67 and 66, the memory 63 isset and a high signal appears on the line 39.

The other input of the memory 63 is connected to the line 35 via afurther delay member 69 and an inverter 60. The delay time of the delaymember 69 is substantially longer and is dependent on the circumstancesduring a standby state of the overall system which will be described indetail hereinafter. It is to be noted that in this standby state apotential higher than the operating voltage occurs on the line 12, evenin the absence of a fault, so that the memory 63 is always set in thestandby state. In this state, however, no data transmission takes placeand a fault signal is not evaluated either.

FIG. 5 shows the construction of the circuit 29 of FIG. 2 in moredetail. The line 37a, carrying a signal if the line 12 isshort-circuited to ground or to the line 11 as described before, isconnected to an input of an OR-gate 71 and of an OR-gate 72. The outputsignal of the OR-gate 72 on the line 79 opens the switch 73, thusinterrupting the connection between the line 31 and the data output 40,so that the signal on the data output 40 is no longer derived from thecomparator 21 in FIG. 2. On the line 78 the OR-gate 71 generates asignal which closes the switch 74 so that the line 32 is then connectedto the data output 40 and hence the signal on the data output is derivedfrom the comparator 22 in FIG. 2. Moreover, the signal on the line 78opens a switch 77 which connects the line 12 to the operating voltage Vcvia the resistor 15. Thus, in case the line 12 is short-circuited toground, a current cannot be dissipated continuously from the operatingvoltage via the resistor 15 or, in case the line 12 is short-circuitedto the line 11, the recessive potential on both lines cannot riseexcessively. Merely a connection remains between the line 12, via theresistor 15 and a very high-valued resistor 17, and the operatingvoltage Vc in order to ensure that the line 12 does not assume anundefined potential after removal of the fault.

The line 38a, carrying a signal if the line 11 is short-circuited to thehigher supply voltage, is also connected to an input of the OR-gate 72,so that in this case the connection between the line 31 and the dataoutput 40 is also interrupted. Moreover, the signal on the line 38adrives a switch 75 which then connects the line 33 to the data output 40and, furthermore, a switch 76 is opened so that the line 11 is no longerconnected to ground via the resistor 14 and hence an unnecessary currentthrough the resistor 14 is avoided. The line 11 is still connected toground merely via the series connection of the resistor 14 and the veryhigh-valued resistor 16; this is done for the same reasons as describedabove for the line 12 and the series connection of the resistors 15 and17. If the short-circuit of the line 11 to the supply voltage is notvery low-impedance and a voltage division occurs in all stationsconnected to the line 11, because of the resistors 16 initiallyconnected to ground, so that because of the tolerances of the thresholdvoltages of the comparators 24 in the stations only one of thesecomparators is switched over and disconnects the resistor 16, thevoltage division changes in such a manner that the voltage on the line11 becomes higher. Consequently, in at least one further station thecomparator 24 will be activated and disconnect the resistor 16 in thisstation etc., until all stations have the same state with a disconnectedresistor 16. The reverse effect occurs if the short-circuit between theline 11 and the supply voltage assumes a higher resistance, so that thecomparator 24 in at least one station is activated in the oppositedirection. In that case all stations again successively assume the samestate. In both cases a kind of hysteresis occurs due to the describedeffect.

The line 39a, carrying a signal if the line 12 is short-circuited to thehigher supply voltage, is connected to an input of the OR-gates 71 and72, that is to say in the same way as the line 37a, so that the switches73 and 77 are opened and the switch 74 is closed and hence the line 32is connected to the data output 40.

It is to be noted that the states on the lines 11 and 12 are determinednot only by the resistors 14 and 15 of the relevant station but also bythe corresponding resistors of the other stations.

A system of the kind set forth is often used in an environment in whichthe source delivering the higher supply voltage contains a limitedamount of energy only. This is the case notably if the described systemis used in a motor vehicle. Therefore, for a system of this kind thereis provided not only a normal transmission mode but also a standby statein which, even though correct reception and transmission of data is notpossible, the data transmitted by other stations can be interpreted as arequest to change over to the normal transmission mode if given criteriaare satisfied. This change-over is also referred to as prompting. Forexample, if no data has been transmitted during a predetermined periodof time, a station can thus be set to a state of very low powerconsumption, i.e. the standby state; however, it can be returned to thenormal transmission state at any time under the control of thetransmission lines. The power consumption in the standby state should beas low as possible, because the overall energy consumption increases inproportion to the number of stations in a system.

The desired minimum power consumption in the standby state, however, isopposed by the fact that in each station the operating voltage for theelectronic circuit is derived from the higher supply voltage, i.e. fromthe battery in the case of a motor vehicle, and a voltage stabilizationcircuit required for this purpose needs, like the further circuit ineach station, a minimum current which is larger than the desired currentin the standby state. Therefore, in the standby state the voltagestabilization circuit is completely switched off, so that an operatingvoltage is not present any longer. Consequently, in the standby statethe line 12 no longer receives the recessive high potential via theresistor 15 in each station. This would not cause faults in the otherswitched-off stations, but it would then no longer be possible for astation which has been set to the normal transmission state, for exampleby a local facility such as a switch, to prompt all other stations bydriving both lines of the bus. The condition that both lines must bedriven for the prompting of the other stations is based on the fact thatin the case of a fault in one line, it should still be possible toprompt all other stations.

FIG. 6 shows a circuit which also enables fault-free operation in thesecircumstances. This Figure shows a station which receives a supplyvoltage via the line 13. The station comprises a control unit 81 whichcontrols not only the transmission and reception of data via the lines11 and 12, but also the setting to the standby state or the transmissionstate. The line 13 is connected to a voltage control circuit 82 whichderives a stabilized operating voltage Vc therefrom for supply to thecontrol unit 81. Moreover, the voltage control circuit 82 can bedisconnected via the line 85 in order to set the station to the standbystate in which the operating voltage Vc substantially disappears.Because the processing of a data transmission via the lines 11 and 12must be operational in the standby state, for this part of the circuit,requiring very little current only, the line 13 is also connecteddirectly to the control unit 81.

In order to ensure that in the standby state of all stations a datatransmission for a prompted station can indeed commence, it must beensured that a recessive high potential is present on the line 12 alsoin the standby state. This is no longer simply possible via the resistor15 if the voltage Vc is absent in the standby state. Therefore, the line13 carrying the higher supply voltage is connected, via a resistor 84,to a switch 83 which connects, under the control of the control unit 81,the two resistors 84 and 15 in series in the standby state and henceproduces a potential on the line 12 which is approximately equal to thesupply voltage on the line 13. This voltage is higher than in the normaltransmission state, but no data transmission is desired in the standbystate. The memory 63 of FIG. 4 is not set in the standby state, becausethe operating voltage is absent.

A station which is prompted by a local condition and commences atransmission first switches over the switch 83 again, so that the line12 in this station is connected, via the resistor 15, to the operatingvoltage Vc which is then also switched on. However, because the line 12in the other stations is still connected to the higher supply voltagevia the resistor 84, the line 12 will initially carry a potential whichis higher than that in the normal transmission state, with the resultthat the memory 63 (FIG. 4) is set in the initially prompted stations.However, as soon as the line 1 has carried the potential correspondingto the normal transmission state for a sufficiently long period of time,corresponding to the delay time of the delay members 69 in theindividual stations, all memories 63 are ultimately reset again. Becausenormal data transmission is also possible in the set state of the memory63, disturbances will not be introduced thereby.

However, faults could appear or be present on the lines 11 and 12 alsoin the standby state of all stations, but such faults may not lead to anincreased power consumption. Therefore, there is provided a faultdetection circuit which is operative in the standby state and is shownin FIG. 7. Therein, the line 11 is connected to two comparators 91 and92 which compare the potential on the line 11 with various thresholdvalues. The comparator 91 checks whether the potential on the line 11exceeds a value which is slightly below the supply voltage on the line13. This is the case if the line 11 is short-circuited to the supplyvoltage. The signal then generated on the line 101 is applied to aninput of an AND-gate 96 via a delay member 95. The output of said gateis connected to the switch 76 in FIG. 5 and isolates the resistor 14from ground, so that in the fault case no current can flow from thesupply voltage via the resistor 14 or the resistors 14 in all stations,because all stations detect the same fault and isolate the resistor 14from ground.

The line 12 carries a high potential in the recessive state as describedabove. However, if this line is short-circuited to ground, in eachstation a current would flow, via the resistors 15 and 84, from thesupply voltage to ground via the resistor 15. The comparator 93 comparesthe potential on the line 12 with a threshold value between the dominantpotential and the recessive potential and outputs a signal if thepotential on the line 12 drops below this threshold value. This signalis applied, via the OR-gate 97 and a delay member 98, to the switch 77in FIG. 5 so that the resistor 15 is no longer connected to the resistor84 in FIG. 6 and hence no current can flow from the supply voltage toground.

If the two lines 11 and 12 are short-circuited to one another, they havea common potential which may be valued between ground and a voltagebelow the supply voltage, depending notably on how many stations havealready reacted to this fault. For detection there is provided thecomparator 92 which compares the potential on the line 11 with athreshold value which is also valued between the dominant and therecessive potential, but is smaller than the threshold value of thecomparator 93. It is thus ensured that at least one of the comparators92 or 93 outputs a signal in the case of a short-circuit between the twolines 11 and 12. The output signal of the comparator 92 is applied to anAND-gate 94, an inhibit input of which is connected to the output of thecomparator 91 because the comparator 92 also supplies an output signalif the line 11 is short-circuited to the supply voltage, in which casethe output signal of the comparator 92 should not be active. Thus, ifonly the lines 11 and 12 are short-circuited to one another, theAND-gate 94 is enabled and the output signals of both comparators 92 and93 are combined in the OR-gate and applied, via the delay member 98, tothe switch 77 in FIG. 5. Moreover, the output signal of the delay member98 is also applied to an inhibit input of the AND-gate 96 in order toprevent disconnection of the two resistors 14 and 15. However, thissituation can occur only in the event of a multiple fault, so that thisconnection to the AND-gate 96, and even the gate itself, can also beomitted.

The function of the circuits described thus far will be explained indetail hereinafter.

Specification

The following fault states should be taken into account:

1. interrupted line 11

2. interrupted line 12

3. short-circuit line 11 to Vbat (supply voltage)

4. short-circuit line 12 to ground

5. short-circuit line 11 to ground

6. short-circuit line 11 to ground

7. short-circuit line 11 to line 12.

These faults should be detected and data transmission shouldnevertheless be possible. The appearance or removal of the faults 1 and2 should not cause any faults in the data stream received. For thefaults 3 to 7 data faults are temporarily permissible during theappearance or the elimination of the line fault, but subsequently thedata transmission must be ensured again. Increased currents andaccompanying higher temperatures should also be avoided.

In the standby state the line 12 carries the potential Vbat. Thus, ingiven circumstances other fault situations occur. The faults liable tocause increased currents in the standby state are the faults 3, 4 and 7.

Signal states

The data transmission takes place while using two different signalpotentials. In the recessive state, no switch 6 or 7 in closed in anystation, and hence the following signal potentials occur:

line 11: ground+ΔU(0 . . . 0.25 V),

line 12: Vc-ΔU(4.5 . . . 5.25 V) in the operating state and Vbat-ΔU(6 .. . 27 V) in the standby state.

In the dominant state, the switches 6 and 7, connected to the lines, areclosed in at least one station, so that the following signal potentialsoccur:

line 11: Vc-ΔU1 (minimum 3.35 V; typically 4 V)

line 12: ground+ΔU1 (maximum 1.4 V; typically 1 V).

Therein, ΔU1 denotes the voltage dropping off across the closed switches6 and 7 due to the current through the terminating resistors. Thetermination of the two lines is distributed across all stations in thesystem. The equivalent resistance of all terminating resistors yieldsapproximately the line impedance.

Problems encountered in fault detection

Line potentials in the fault state cannot always be unambiguouslydistinguished from the potentials during normal data transmission. Forexample, in the case of the fault 5 the line 11 is connected to groundpotential in the same way as in the normal recessive state. In the caseof the fault 4 the line 12 is connected to ground potential in the sameway as in the dominant state. The large ground offset which may occurbetween the stations of the system makes the problem of lack ofdistinction more acute. Only the faults 3 and 6 lead to line potentialswhich can be unambiguously distinguished from those occurring during thenormal data transmission. Other faults, which cannot be distinguished inthe rest state, that is in the absence of data transmission, however,must be taken into account differently. For example, if the start of adata series is transmitted in the presence of a fault 1, the two linesare first recessive and only the line 12 then becomes dominant, afterwhich transmission can take place only via the non-faulty line 12. Onthe other hand, if the fault 4 occurs while both lines are recessive,the line 12 again enters the dominant state, but the further datatransmission should take place via the line 11. Therefore, it must bepossible to distinguish these two faults from one another; however, thiscan be achieved only by an additional expenditure.

Fault analysis

Three comparators 21, 22 and 23 are used for the reception of data. Thedifferential threshold voltage of the comparator 21 is fixed at -2.8 V,so that the dominant state of one of the two lines alone as well as ofboth lines together leads to a dominant signal on the comparator output.The comparator 22 evaluates only the state of the line 11 and has athreshold voltage of 1.8 V, whereas the comparator 23 evaluates only thestate of the line 12 and has a threshold voltage of 3.0 V.

In the fault-free state, the data is received or evaluated via thecomparator 21. The differential reception enhances the reliability ofthe data transmission in the case of ground offset between the stationsand electromagnetic compatibility disturbances.

Because of the described choice of the threshold voltage of thecomparator 21, the faults 1, 2 and 5 are tolerated without further stepsbeing required. This is important because even in the case of staticfaults, the faults 1 and 2 possibly appear as recurrent faults. This isdue to the fact that the position of the instantaneously transmittingstation with respect to the fault location differs each time. In orderto enable the fault to be signaled nevertheless, it must indeed bedetected. This is achieved by comparing the output signals of thecomparators 22 and 23, produced by the two lines alone, with the signaloutput by the comparator 21 which evaluates the differential signal ofthe two lines. To this end, the signal edges at the comparator 21 arecounted in two separate counters; an edge at the comparators 22 or 23always resets the associated counter immediately.

Thus, if the comparator 21 outputs, for example seven edges insuccession and one of the comparators 22 or 23 does not output any edgeduring the same period of time, a fault is detected. It is considered tohave been removed when the relevant comparator outputs an edge again.

In the case of the fault 3 the line 11 carries the potential of thesupply voltage; this is unambiguously detected by the comparator 24 viaits threshold voltage of 7.3 V with respect to ground. The output signalof the comparator is stored, via a filter having a delay time of from 10to 60 μs, in the associated memory in order to avoid activation due topossible fault signals which briefly exceed the threshold voltage. Whenthe fault is removed, the memory is reset if the comparator does notoutput a signal for at least a predetermined period of time, i.e. theline 11 carries a potential below said threshold voltage, or even betterby a signal at the comparator 21 since the line 11 then even carriesrecessive potential.

In the case of the fault 6, the line 12 carries the potential of thesupply voltage which is detected by the comparator 25, also having athreshold voltage of 7.3 V with respect to ground. The output signalthereof sets, again via a filter, an associated memory which is resetagain upon removal of the fault, and hence upon termination of theoutput signal of the comparator 25, be it via a filter having asubstantially longer delay time of from 150 to 1000 μs. This longerdelay time serves to avoid unnecessary switching over of the memory by adata transmission during the switching-over from the standby state tothe normal mode.

In the case of a fault 4 the line 12 is short-circuited to ground sothat it continuously carries a dominant signal, whereas in the case ofthe fault 7 both lines are short-circuited and hence always one of thetwo lines carries a dominant signal, so that the comparator 21continuously outputs a dominant signal. If this signal prevails for apredetermined period of time, a further memory is set. Thispredetermined period of time must be longer than the duration of themaximum number of dominant bits during a data transmission. The end ofthe fault 4 or 7 is detected via a sufficiently long recessive outputsignal at the comparator 21, so that the relevant memory is reset.

The faults are detected independently of one another, but many faultslead to the phenomenon that upon occurrence of one fault, or afterexpiration of all time conditions, several faults are simultaneouslydetected in the steady state. A priority circuit, having the priorityorder fault 3 fault 6, fault 4 or 7, signals exactly one of the feasiblefaults.

Fault treatment

In the case of a fault, the non-disturbed line is used for the furtherdata transmission in as far as possible. Depending on the faultdetected, therefore, the outputs of the comparators 22 or 23, evaluatingthe potential transitions on the lines 11 or 12 alone, are connected tothe data output instead of the output of the comparator 21. Moreover, inthe case of some faults one of the terminating resistors is disconnectedand the driving of one of the transmitter switches is prevented.

In the case of fault 3, the line 11 becomes inoperative and thecomparator 23 for the line 12 is connected to the data output. Theterminating resistor of the line 11 is disconnected and the driving ofthe transmission switch for the line 11 is inhibited.

In the case of the fault 6, the line 12 is disturbed; consequently, theoutput of the comparator 22, evaluating the line 11, is connected to thedata output, the terminating resistor of the line 12 is disconnected andthe driving of the transmission switch for the line 12 is inhibited.

In the case of the fault 7, both lines are short-circuited, so that thedriving and evaluation of the signals of one of the two lines isinterrupted. This is effectively the line 12, so that the further datatransmission takes place via the line 11, the terminating resistor forthe line 12 then being disconnected and the driving of the transmissionswitch for the line 12 being inhibited. These steps correspond to thefault 6, and the output of the comparator 22 is connected to the dataoutput. The same steps are also taken for the fault 4 where the line 12is disturbed.

Fault treatment in the standby state

No data transmission is possible in the standby state and the system isin a state of low power consumption. In this state, the faults 1, 2, 5and 6 do not cause increased power consumptions. Merely the faults 3, 4and 7 must be detected so as to avoid increased power consumption. Tothis end, three further comparators 91, 92 and 93 are used, thecomparators 91 and 92 evaluating the state of the line 11 whereas thecomparator 93 evaluates the state of the line 12. The comparator 91 hasa threshold value which is approximately 2 V below the supply voltage;the comparator 92 has a threshold value of approximately 2 V in order todetect the dominant state on the line 11, and the comparator 93 has athreshold voltage of approximately 3 V in order to detect the dominantstate on the line 12.

In the case of the fault 3, the line 11 is short-circuited to the supplyvoltage, so that the comparator 91 is activated. The terminatingresistor of the line 11 is then disconnected via a time delay.

In the case of the fault 4, the line 12 is short-circuited to ground, sothat the comparator 93 is activated. Therefore, the terminating resistorof the line 12 is also disconnected after a time delay.

When the fault 7 is detected, a larger voltage range of the supplyvoltage must be taken into account. Depending on the number of stationsin the system, the resultant terminating resistance amounts to fromapproximately 100 to 200 ohms for the line 11 to ground and from 250 to5000 ohms for the line 12 to the supply voltage. As a result, voltagesof from approximately 0.3 to 8 V are reached in the case of the fault 7,i.e. in the case of a short-circuit between the lines 11 and 12.Consequently, at least one of the comparators 92 or 93 generates anoutput signal. An OR-combination of these comparator outputs disconnectsthe terminating resistor of the line 12 via a time delay. Because of thedistributed disconnection of these terminating resistors in the system,the potential on the two short-circuited lines 11 and 12 increases withrespect to ground. Because of the overlapping threshold voltages at thecomparators 92 and 93 it is ensured that at least one of thesecomparators outputs an output signal during the traversing of thevoltage range. After all terminating resistors have been disconnected,the comparator 93 ultimately supplies an output signal.

It is to be noted that in the case of the fault 3 the comparator 92 alsogenerates an output signal, even though the terminating resistor of theline 11 is disconnected in the case of this fault. Therefore, the outputsignal of the comparator 92 is latched by the output signal of thecomparator 91. Additional latching of the disconnection signal for theterminating resistor of the line 12 by the signal for disconnection ofthe terminating resistor for the line 11 ensures that the twoterminating resistors are not disconnected simultaneously in any faultcase or in any transitional state.

It is thus ensured that in the operating state a logically stillexisting possibility for data transmission is utilized in any faultcase, whereas in the standby state increased power consumption isreliably prevented in any fault case.

We claim:
 1. A system for the transmission of binary data between anumber of stations which are interconnected via a common first line anda common second line, the first line having a low potential and thesecond line a high potential for one logic value of the binary datawhereas the first line has a high potential and the second line a lowpotential for the other logic value of the binary data, the logic valueof the binary data being derived from the potential of at least oneline, for output on a data output, said system comprising:a firststation including a first comparator coupled to both lines andconfigured to subtract the potential on the first line from thepotential on the second line and provide an output signal of a firstvalue via a first comparator output if the difference formed by thesubtraction exceeds a first threshold value, said first threshold valuebeing chosen so that the output signal of the first comparator alsochanges its value if a potential transition occurs on only one of thetwo lines and the other line has a potential corresponding to the onelogic value of the binary data.
 2. A system as claimed in claim 1, saidfirst station comprising:a second comparator coupled to the first lineand configured to generate an output signal of the first value on asecond comparator output if the potential on the first line is below asecond threshold value a first memory; first delay member having a firstdelay time, wherein said first memory is coupled to the first comparatoroutput via said first delay member; and a switch, wherein an output ofsaid memory is coupled to said switch for switching the data output fromthe first comparator output to the second comparator output if theoutput signal on the first comparator output continuously has the firstvalue for a period of time corresponding to the first delay time.
 3. Asystem as claimed in claim 2, said system comrpising:a second delaymember having a second delay time, wherein the first memory in saidfirst station is also coupled, via said second delay member, to thefirst comparator output such that the first memory switches over theswitch such that the data output is switched back from the secondcomparator output to the first comparator output if the output signal onthe first comparator output does not have the first value for a periodof time corresponding to the second delay time.
 4. A system as claimedin claim 3, said system comprising:a supply voltage; an electriccircuit; and a third line, said first station comprising:a thirdcomparator; a fourth comparator; a fifth comparator; a second memory; athird memory; and a third delay member having a third delay time,wherein said supply voltage is configured to provide a lower operatingvoltage in at least some stations for operation of said electric circuitin the stations to drive the first and the second line, at least a partof these stations being connected via said third line which carries thesupply voltage, the third comparator being coupled to the second line togenerate an output signal of the first value on a third comparatoroutput if the potential on the second line exceeds a third thresholdvalue, the fourth comparator being coupled to the first line and thefifth comparator being coupled to the second line, each of the fourthand fifth comparators generating an output signal of a first value on afourth and a fifth comparator output, respectively, if the potential onthe line coupled to the relevant comparator exceeds a fourth thresholdvalue which is valued between the operating voltage and the supplyvoltage, each of said second and third memories comprising a first and asecond input and an output, the first input of the second memory beingconnected to the first comparator output, the second input of the secondmemory being connected to the fourth comparator output, the first inputof the third memory being connected to the fifth comparator output, thesecond input of the third memory being connected to the fifth comparatoroutput via said third delay member the output of the second memory iscoupled to the switch to couple the third comparator output to the dataoutput, the output of the third memory being coupled to the switch tocouple the second comparator output to the data output.
 5. A system asclaimed in claim 4, said system comprising a fault indication output,said first station comprising:a first counter; and a second counter,each of said first and second counters comprising a count input, a resetinput and a count output, the count input of said first and secondcounters being coupled to the first comparator output, the reset inputof the first counter being coupled to the second comparator output, thereset input of the second counter being coupled to the third comparatoroutput, and the count output of said first and second counters and theoutput of the first, second, and third memories being coupled to thefault indication output.
 6. A system as claimed in claim 3, wherein eachline in each station comprises:an associated switch coupled to thepotential for the other logic value of the binary data; and a drivecircuit configured to close said switch and said associated switch totransmit the other logic value of the binary data in the fault-freecase, wherein the case of a fault where at least one of the two lines islow-impedance connected to a voltage which at least deviates from thepotential corresponding to the other logic value of the binary data, thedrive circuit is configured to prevent the closing of the switchassociated with the relevant line.
 7. A system as claimed in claim 2,said system comprising:a supply voltage; an electric circuit; and athird line, said first station comprising:a third comparator; a fourthcomparator; a fifth comparator; a second memory; a third memory; and athird delay member having a third delay time, wherein said supplyvoltage is configured to provide a lower operating voltage in at leastsome stations for operation of said electric circuit in the stations todrive the first and the second line, at least a part of these stationsbeing connected via said third line which carries the supply voltage,the third comparator being coupled to the second line to generate anoutput signal of the first value on a third comparator output if thepotential on the second line exceeds a third threshold value, the fourthcomparator being coupled to the first line and the fifth comparatorbeing coupled to the second line, each of the fourth and fifthcomparators generating an output signal of a first value on a fourth anda fifth comparator output, respectively, if the potential on the linecoupled to the relevant comparator exceeds a fourth threshold valuewhich is valued between the operating voltage and the supply voltage,each of said second and third memories comprising a first and a secondinput and an output, the first input of the second memory beingconnected to the first comparator output, the second input of the secondmemory being connected to the fourth comparator output, the first inputof the third memory being connected to the fifth comparator output, thesecond input of the third memory being connected to the fifth comparatoroutput via said third delay member the output of the second memory iscoupled to the switch to couple the third comparator output to the dataoutput, the output of the third memory being coupled to the switch tocouple the second comparator output to the data output.
 8. A system asclaimed in claim 7, said system comprising a fault indication output,said first station comprising:a first counter; and a second counter,each of said first and second counters comprising a count input, a resetinput and a count output, the count input of said first and secondcounters being coupled to the first comparator output, the reset inputof the first counter being coupled to the second comparator output, thereset input of the second counter being coupled to the third comparatoroutput, and the count output of said first and second counters and theoutput of the first, second, and third memories being coupled to thefault indication output.
 9. A system as claimed in claim 2, wherein eachline in each station comprises:an associated switch coupled to thepotential for the other logic value of the binary data; and a drivecircuit configured to close said switch and said associated switch totransmit the other logic value of the binary data in the fault-freecase, wherein the case of a fault where at least one of the two lines islow-impedance connected to a voltage which at least deviates from thepotential corresponding to the other logic value of the binary data, thedrive circuit is configured to prevent the closing of the switchassociated with the relevant line.
 10. A system as claimed in claim 1,said system comprising:a supply voltage; an electric circuit; and athird line, said first station comprising:a third comparator; a fourthcomparator; a fifth comparator; a second memory; a third memory; and athird delay member having a third delay time, wherein said supplyvoltage is configured to provide a lower operating voltage in at leastsome stations for operation of said electric circuit in the stations todrive the first and the second line, at least a part of these stationsbeing connected via said third line which carries the supply voltage,the third comparator being coupled to the second line to generate anoutput signal of the first value on a third comparator output if thepotential on the second line exceeds a third threshold value, the fourthcomparator being coupled to the first line and the fifth comparatorbeing coupled to the second line, each of the fourth and fifthcomparators generating an output signal of a first value on a fourth anda fifth comparator output, respectively, if the potential on the linecoupled to the relevant comparator exceeds a fourth threshold valuewhich is valued between the operating voltage and the supply voltage,each of said second and third memories comprising a first and a secondinput and an output, the first input of the second memory beingconnected to the first comparator output, the second input of the secondmemory being connected to the fourth comparator output, the first inputof the third memory being connected to the fifth comparator output, thesecond input of the third memory being connected to the fifth comparatoroutput via said third delay member the output of the second memory iscoupled to the switch to couple the third comparator output to the dataoutput, the output of the third memory being coupled to the switch tocouple the second comparator output to the data output.
 11. A system asclaimed in claim 10, said system comprising a fault indication output,said first station comprising:a first counter; and a second counter,each of said first and second counters comprising a count input, a resetinput and a count output, the count input of said first and secondcounters being coupled to the first comparator output, the reset inputof the first counter being coupled to the second comparator output, thereset input of the second counter being coupled to the third comparatoroutput, and the count output of said first and second counters and theoutput of the first, second, and third memories being coupled to thefault indication output.
 12. A system as claimed in claim 11, whereineach line in each station comprises:an associated switch coupled to thepotential for the other logic value of the binary data; and a drivecircuit configured to close said switch and said associated switch totransmit the other logic value of the binary data in the fault-freecase, wherein the case of a fault where at least one of the two lines islow-impedance connected to a voltage which at least deviates from thepotential corresponding to the other logic value of the binary data, thedrive circuit is configured to prevent the closing of the switchassociated with the relevant line.
 13. A system as claimed in claim 11,said system comrpising;a first resistor; a second resistor; a firstswitch; and a second switch, wherein the first line in said firststation is coupled to the low potential via said first resistor, thesecond line is coupled to the high potential via said second resistor,said first switch is connected in series with the first resistor, saidsecond switch is connected in series with the second resistor, theoutput of the second memory is coupled to the first switch, and theoutputs of the first memory and the third memory are coupled together tothe second switch.
 14. A system as claimed in claim 10, said systemcomrpising:a first resistor; a second resistor; a first switch; and asecond switch, wherein the first line in said first station is coupledto the low potential via said first resistor, the second line is coupledto the high potential via said second resistor, said first switch isconnected in series with the first resistor, said second switch isconnected in series with the second resistor, the output of the secondmemory is coupled to the first switch, and the outputs of the firstmemory and the third memory are coupled together to the second switch.15. A system as claimed in claim 14, said system comprising:a thirdresistor; a sixth comparator; and a seventh comparator, wherein saidsystem is configured such that in a standby state, in which the powerconsumption is substantially reduced by switching off the operatingvoltage for the comparators, the memories and the counters, the secondline is coupled only to the higher supply voltage, via said thirdresistor, and wherein said sixth and seventh comparators are active inthe standby state, said sixth comparator being coupled to the first lineto generate an output signal of a first value on a sixth comparatoroutput if the potential on the first line exceeds a predetermined fifththreshold value, the sixth comparator output being coupled to the firstswitch, said seventh comparator being coupled to the second line togenerate an output signal of a first value on a seventh comparatoroutput if the potential on the second line drops below a predeterminedsixth threshold value, the seventh comparator output being coupled tothe second switch.
 16. A system as claimed in claim 15, said systemcomprising an eigth comparator configured to be active in the standbystate and is coupled to the first line to generate an output signal of afirst value on an eigth comparator output if the potential on the firstline exceeds a predetermined seventh threshold value, the eigthcomparator output also being coupled to the first switch if the sixthcomparator output does not generate an output signal of the first value.17. A system as claimed in claim 10, wherein each line in each stationcomprises:an associated switch coupled to the potential for the otherlogic value of the binary data; and a drive circuit configured to closesaid switch and said associated switch to transmit the other logic valueof the binary data in the fault-free case, wherein the case of a faultwhere at least one of the two lines is low-impedance connected to avoltage which at least deviates from the potential corresponding to theother logic value of the binary data, the drive circuit is configured toprevent the closing of the switch associated with the relevant line. 18.A system as claimed in claim 1, wherein each line in each stationcomprises:an associated switch coupled to the potential for the otherlogic value of the binary data; and a drive circuit configured to closesaid switch and said associated switch to transmit the other logic valueof the binary data in the fault-free case, wherein the case of a faultwhere at least one of the two lines is low-impedance connected to avoltage which at least deviates from the potential corresponding to theother logic value of the binary data, the drive circuit is configured toprevent the closing of the switch associated with the relevant line. 19.A system as claimed in claim 18, said system comrpising:a firstresistor; a second resistor; a first switch; and a second switch,wherein the first line in said first station is coupled to the lowpotential via said first resistor, the second line is coupled to thehigh potential via said second resistor, said first switch is connectedin series with the first resistor, said second switch is connected inseries with the second resistor, the output of the second memory iscoupled to the first switch, and the outputs of the first memory and thethird memory are coupled together to the second switch.
 20. A stationfor a system as claimed in claim 1.